The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
During the photolithography step of semiconductor production, light energy is applied through a photomask onto the photoresist material previously deposited on the wafer to define circuit patterns which will be etched in a subsequent processing step to define the circuits on the wafer. Because these circuit patterns on the photoresist represent a two-dimensional configuration of the circuit to be fabricated on the wafer, minimization of particle generation and uniform application of the photoresist material to the wafer are very important. By minimizing or eliminating particle generation during photoresist application, the resolution of the circuit patterns, as well as circuit pattern density, is increased.
A reticle is a transparent plate patterned with a circuit image to be formed in the photoresist coating on the wafer. A reticle contains the circuit pattern image for only a few of the die on a wafer, such as four die, for example, and thus, must be stepped and repeated across the entire surface of the wafer. In contrast, a photomask, or mask, includes the circuit pattern image for all of the die on a wafer and requires only one exposure to transfer the circuit pattern image for all of the dies to the wafer. Reticles are used for step-and-repeat steppers and step-and-scan systems found in wafer fabrication.
Reticles and photomasks must remain meticulously clean for the creation of perfect images during its many exposures to pattern a circuit configuration on a substrate. Reticles and photomasks may be easily damaged such as by dropping, by the formation of scratches on the reticle or photomask surface, electrostatic discharge (ESD), and particles. ESD can cause discharge of a small current through the chromium lines on the surface of the reticle or photomask, melting a circuit line and destroying the circuit pattern. The terms “photomask” and “reticle” shall be used interchangeably herein.
A photomask blank 10 shown in FIG. 1A is used to fabricate a conventional photomask 10a shown in FIG. 1B. As shown in FIG. 1A, the mask blank 10 includes a transparent mask substrate 12 which is typically quartz or fused silica, an opaque patterning layer 14 such as chromium provided on the mask substrate 12, and a photoresist layer 16 on the patterning layer 14. Throughout fabrication of the photomask 10a, the photoresist layer 16 is exposed, baked and developed, respectively, to form exposure openings (not shown) therein. A patterned layer 14a, having exposure openings 15 as shown in FIG. 1B, is formed by etching the patterning layer 14 according to the circuit pattern of the overlying photoresist layer 16.
Throughout the course of using, transferring or storing a reticle or photomask in a semiconductor production facility, static electricity has a tendency to accumulate and form an electric field on the mask. Voltage differences are frequently established between adjacent portions of a patterned chromium layer on a photomask, resulting in electrostatic discharges on the photomask. These electrostatic discharges on the surface of the photomask may burn or melt the patterned chromium layer. Consequently, the circuit pattern image transferred through the mask can be distorted, compromising pattern reliability and causing severe yield loss.
Accordingly, a novel anti-ESD photomask blank having a conductive layer for the fabrication of anti-ESD photomasks is needed to maintain all portions of a patterned chromium layer on a photomask at the same voltage potential and prevent electrostatic discharges from occurring on the photomask.